The Hong Kong Polytechnic University (PolyU) announced a breakthrough in transistor technology that could redefine the future of microelectronics. A research team led by Prof. Jianhua HAO, Head of the Department of Physics and Materials and Chair Professor of Materials Physics and Devices, has developed a novel tunnelling field-effect transistor (TFET) using 2D nanomaterials. The innovation overcomes the physical 'Boltzmann limit,' a barrier that has long constrained the energy efficiency of traditional transistors.
Conventional transistors rely on thermionic emission, which requires a minimum gating voltage of 60 millivolts (mV). This limitation, known as the Boltzmann limit, makes subthreshold swing (SS) values below 60 mV per decade impossible at room temperature, thereby restricting progress in high-performance electronics. The PolyU-led team, collaborating with the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design, has engineered a TFET that adopts quantum tunnelling to bypass this boundary.
Prof. Hao stated, "By adopting quantum tunnelling, our TFET breaks through this boundary, paving the way for ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications." The research findings were published in the prestigious scientific journal Science.
The team created an ultra-thin heterostructure of alternating 2D bismuth and indium selenide layers using pulsed laser deposition. By precisely controlling the layer structure, the normally semi-metallic bismuth transforms into a semiconductor in its 2D form, enabling charge carriers to tunnel efficiently into indium selenide through quantum tunnelling. The resulting TFET achieved SS values well below the 60 mV per decade limit, operating at room temperature on silicon substrates. The device required a gate-voltage range of only 160 mV, compared to the 800 mV originally needed, a fivefold reduction in voltage.
This breakthrough resolves a long-standing challenge in experimental TFETs: delivering a high output current alongside an exceptionally high ON/OFF current ratio. This combination is critical for driving multiple downstream logic gates and reducing circuit delay, making the technology viable for practical integrated circuits.
The implications are significant for the semiconductor industry and beyond. As the demand for energy-efficient computing grows, especially with the rise of artificial intelligence (AI) and machine learning, the need for transistors that consume less power while delivering higher performance is paramount. This TFET technology could lead to more efficient AI chips, longer battery life in portable devices, and reduced energy consumption in data centers. It also offers a pathway to continue scaling down transistor sizes, addressing the slowdown in Moore's law.
The collaboration between PolyU and other leading institutions underscores the global effort to push the boundaries of semiconductor technology. With this advancement, the team has provided a foundation for future innovations in ultra-low-power electronics, potentially transforming industries reliant on high-performance computing.
